Senior/Staff SoC RTL Integration Engineer

Leading the design, implementation, and integration of complex digital blocks and IPs into SoCs, focusing on high-quality Verilog/SystemVerilog, PPA(Power,Performance,Area) and ensuring seamless cross-functional collaboration (PD, DV, Firmware) for first-time silicon success, mentoring junior engineers, and driving new methodologies.
Job Responsibilities
SOC Integration: Lead integration of major subsystems (PCIe, CXL, NoC) and IP blocks, resolving inter-IP issues.
Verification & Quality: Drive rigorous RTL quality checks (Lint, CDC, Formal), simulation, and support DV teams.
Optimization: Optimize designs for Power, Performance, and Area (PPA) targets, experience low-power techniques (UPF) is a plus.
Front-End Flow Ownership: Drive Lint, CDC, Synthesis, DFT, RDC, and Formality checks, often scripting automation (Python) and resolving issues.
Cross-Functional Leadership: Collaborate with Verification, Physical Design, Firmware, and Validation teams, bridging gaps and ...