Re
Posted:
June 06, 2026
Location:
Zurich, Switzerland, Switzerland
Job Description
Staff Analog Design Engineer (f/m/d)
Job Description
We are looking for a Staff Analog Design Engineer to join our team in Zürich, working on next-generation mixed-signal ICs for wireless power and power management (PMIC) applications.
In this role, you will take end-to-end ownership of major analog IPs and contribute at both architecture and implementation level, from concept definition through mass production silicon.
Key Responsibilities
+ Lead the definition, design, and ownership of complex analog and mixed-signal IPs, such as:
+ PMIC building blocks (LDOs, references, regulators, amplifiers)
+ Wireless power-related analog IPs
+ High-performance ADC/DAC interfaces and analog front-ends
+ Contribute to system-level and architecture definition in close collaboration with digital, firmware, and system teams
+ Perform transistor-level design, simulation, and optimization, including:
+ P...
Job Description
We are looking for a Staff Analog Design Engineer to join our team in Zürich, working on next-generation mixed-signal ICs for wireless power and power management (PMIC) applications.
In this role, you will take end-to-end ownership of major analog IPs and contribute at both architecture and implementation level, from concept definition through mass production silicon.
Key Responsibilities
+ Lead the definition, design, and ownership of complex analog and mixed-signal IPs, such as:
+ PMIC building blocks (LDOs, references, regulators, amplifiers)
+ Wireless power-related analog IPs
+ High-performance ADC/DAC interfaces and analog front-ends
+ Contribute to system-level and architecture definition in close collaboration with digital, firmware, and system teams
+ Perform transistor-level design, simulation, and optimization, including:
+ P...
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Submit your application for the Staff Analog Design Engineer (f/m/d) position at Renesas.
Apply Now Save for LaterJob Overview
Job Type:
Full-time
Location:
Zurich, Switzerland
Posted:
June 06, 2026
Deadline:
June 11, 2026