SysVerilog UVM Verification Engineer (FPGA/ASIC) Mandarin

A technology company in Penang is seeking a verification engineer with expertise in FPGA/ASIC design. The role involves performing pre-Si verification, defining test plans, and developing test benches using System Verilog/UVM. The candidate must have a BSEE/MSEE/PhD with at least 3 years of relevant experience. Mandarin-speaking is essential. The position is onsite, and experienced candidates may also be considered for a KL location.
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