Technical Lead: RTL-to-GDSII Backend & Tapeout

Synthara AG
Full-time Zürich, Zürich Ingenieurwesen und Technik
Posted:
March 01, 2026
Location:
Zürich, Zürich, Switzerland

Job Description

A semiconductor firm is seeking a technical leader for ASIC physical design in Zürich. This role demands over a decade of experience, including successful tapeouts. You'll define methodologies, manage a backend team of engineers, and ensure quality metrics are met. Ideal candidates will have expertise in major tool chains like Synopsys or Cadence and possess scripting skills for automation. This position promises a challenging yet rewarding environment focused on innovation and integrity.
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Job Overview

Job Type: Full-time
Location: Zürich, Switzerland
Posted: March 01, 2026
Deadline: April 10, 2026