Verification Engineer: UVM Testbench & Automation

A technology firm in Penang is seeking candidates to develop testbench components and automate validation environments. Candidates will collaborate with architects and design engineers to define test plans and write/debug tests in UVM/C++. Knowledge in C, Python, and shell scripting is required. Fresh graduates are welcome to apply. This role is exclusive to Malaysia-based applicants offering a great opportunity for both new and experienced professionals.
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